IBM unveiled their next generation POWER7 processors at Hot Chips Conference. POWER7 processors will come in 8-, 6- and 4-core configurations with 1.2 billion transistors. The processor will have shared 32MB L3 cache, 256KB of L2 cache for each core and 32 KB of instruction and data cache for each core. IBM hasn’t specified the clock speed of the upcoming processors, but each eight-core processor will be able to execute 32 threads and the POWER7 will scale up to 32 sockets for 1,024 threads in total.

IBM will use 45nm process technology to manufacture POWER7 chips and will package chips differently for different applications, for example a single-chip organic package for 2p and 4p racks, a single-chip glass ceramic package for mid range arrays with two memory controllers, and a quad-chip multi-chip module for compute-intensive apps with eight memory controllers.

Each core of POWER7 chip will have 2 fixed-point units; 2 load-store units; 4 double-precision floating point units; 1 each of branch, condition register, and vector units; and a 6-wide dispatch. These improvements will significantly increase POWER7’s performance when compared to POWER6 chips. IBM says that there will be about 20 percent across the board improvement on a per-core basis, and 4X to 5X performance improvement when compared chip-to-chip.

Advancements made in high-end computing normally trickle down to desktop and laptop level in about two-three years. Already we are seeing integrated memory controllers and L3 cache in desktops processors, soon we will see more than 2 threads per core in desktops processors, like 4 threads per core in POWER7. IBM hasn’t yet announced when they will start shipping the new POWER7 processors.
[Via ExtremeTech]